The present invention generally relates to synchronizing signal detecting circuits in digital signal transmitting systems, and more particularly to a synchronizing signal detecting circuit for accurately detecting a synchronizing signal from digital signals which are time-sequentially multiplexed and transmitted in terms of blocks (frames), where each block comprises a synchronizing signal and digital data.
Systems have been reduced to practice for recording information signals on a spiral track on an information signal recording medium (hereinafter simply referred to as a disc) as rows of time-sequential and intermittent pits, and for reproducing the recorded information signals from such a disc. The recorded information signals are reproduced from the disc as variations in the electrostatic capacitance between the disc and an electrode of a reproducing element, or are reproduced from the disc by use of the variation in the intensity of light reflected from or transmitted through the disc. The information signals may be made up sole of digital audio signals, or may be made up of digital audio signals and a digital video signal which is related to a still picture or a partially moving picture and is added to the digital audio signals as a supplementary information. As will be described later on in the specification in conjunction with the drawings, the digital signals are transmitted in terms of blocks (frames) in such systems. In one block, an 8-bit synchronizing signal having a fixed pattern for indicating the beginning of a block (frame), four channels of digital data (data related solely to the digital audio signals or data related to the digital audio signals and the digital video signal, as described before) each having 16 bits and arranged subsequent to the 8-bit synchronizing signal, two 16-bit error correcting codes, a 23-bit error checking code (cyclic redundancy check code), a 1-bit data corresponding to one bit of a control signal having a total of 196 bits, for example, and a 2-bit spare data often referred to as user's bits, are time-sequentially and successively arranged.
One block (frame) of the digital signals from the synchronizing signal bits to the user's bits, amount to a total of 130 bits. The digital signals have a repetition frequency of 44.1 kHz which is the same as the sampling frequency, for example. The digital signals are transmitted serially at a transmission bit rate of 5.733 Mb/sec, by being time-sequentially multiplexed in terms of blocks (frames). The time-sequentially multiplexed digital signal is an NRZ (non return to zero) signal. This NRZ signal is subjected to a self-clocking digital modulation such as an MFM (modified frequency modulation) or a PM (3-position modulation, or is subjected to a data scrambling by performing a modulo-2 addition with an M-sequence (maximum length sequence) code. The NRZ signal which is subjected to the digital modulation or the data scrambling, is further subjected to a frequency modulation, or the NRZ signal is simply subjected to a frequency modulation without being subjected to the digital modulation. The modulated digital signal is recorded on the disc as rows of intermittent pits by use of a light beam or the like.
In a reproducing apparatus which plays the disc described heretofore, a reproduced digital signal is obtained by subjecting a signal which is reproduced from the disc to a frequency demodulation. The reproduced digital signal has the construction described before. A high-frequency clock signal (having a frequency in the range of 5.733 MHz, for example) which is in phase with the reproduced digital signal, is reproduced from the reproduced digital signal in a clock reproducing circuit. The detection of the synchronizing signal within the reproduced digital signal and the write-in of data into a memory circuit, are performed based on the reproduced clock signal.
A data (false synchronizing signal) having the same pattern as the synchronizing signal, sometimes exists in a signal duration of the digital signals excluding the duration of the synchronizing signal. Conventionally, in a synchronizing signal detecting circuit in a system which transmits the digital signals, the above false synchronizing signal was erroneously detected as it were the synchronizing signal. Consequently, there was a problem in that it was impossible to correctly demodulate the data because of the erroneous detection of the synchronizing signal. In addition, there was a conventional synchronizing signal detecting circuit which employed a counter and was designed to detect the synchronizing signal with a constant period even when a dropout occurred in the synchronizing signal. However, this conventional synchronizing signal detecting circuit also detected the false synchronizing signal, and resulted in an erroneous resetting of the counter when such an erroneous detection was performed. In other words, the false synchronizing signal was erroneously detected as it were the synchronizing signal, and there was a problem in that the data could not be demodulated correctly.